This invention relates in general to a time-space-time (T-S-T) telecommunications switching systems and in particular to an interface arrangement compensating for a system clock skew and a cable delay during transmission of communication information between a transmitting and receiving stage of a T-S-T digital switching system.
Time-space-time (T-S-T) switching systems are a configuration of digital switching elements providing both time and space translation between channels of time division multiplexed (TDM) telecommunications transmission lines. The T-S-T network of a switching system interconnects digital TDM communication lines with TDM communication involving the sharing of a single transmission paths, individually, in time, to provide multiple channels in a single transmission medium. The construction of such a T-S-T network comprises the connection of a spacial stage between the two time stages.
These networks normally operate at very high transmission rates. For example, in a T-S-T network where a single path through the network is divided into 386 channels or time slots the transmission of all 386 channels can occur in 125 microseconds. Therefore, each time slot has a duration of 324 nanoseconds.
Since the transmission from one stage to another requires timing synchronization, any delays introduced between the transmitting and receiving stages will affect the synchronization and therefore cause loss of channels.
The timing delays may be caused by timing skew between identical signals in different stages. Long cables used between stages can also introduce propagation delays. For example, a 100 ft. cable can introduce 178 nanoseconds of delay between a transmitting and receiving stage.
Therefore, the interface of the present invention compensates for timing delays between a transmitting and receiving stage of a T-S-T digital switching system.